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Api
Cardiff
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Strong knowledge in the application of relevant design standards and guidelines (API, AISC, OCIMF, BS 6349, Eurocode, PIANC to name a few)
Strong knowledge in the application of relevant design standards and guidelines (API, AISC, OCIMF, BS 6349, Eurocode, PIANC to name a few)
Description - Hey Im Pete, Chief Revenue Officer at Pinpoint. Were a high-growth HR tech startup building and selling software that helps in-house recruitment teams attract, hire, and onboard the right talent. Today, we have a strong foundation in place, with a mature product, rapid growth, strong productmarket fit, and happy customers. To date, Ive been the one leading technical discovery, building Proofs of Concept (PoCs), and unblocking complex deals. Its worked, but it doesnt scale. As we handle a higher volume of larger, more complex deals, we need dedicated technical horsepower embedded in Sales. Thats where you come in. Were hiring our first Solutions Engineer to partner closely with AEs leading technical discovery, designing tailored solutions, and building proofs of concept that prove we can deliver.
Description - Hey Im Pete, Chief Revenue Officer at Pinpoint. Were a high-growth HR tech startup building and selling software that helps in-house recruitment teams attract, hire, and onboard the right talent. Today, we have a strong foundation in place, with a mature product, rapid growth, strong productmarket fit, and happy customers. To date, Ive been the one leading technical discovery, building Proofs of Concept (PoCs), and unblocking complex deals. Its worked, but it doesnt scale. As we handle a higher volume of larger, more complex deals, we need dedicated technical horsepower embedded in Sales. Thats where you come in. Were hiring our first Solutions Engineer to partner closely with AEs leading technical discovery, designing tailored solutions, and building proofs of concept that prove we can deliver.
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Principal Supportability Engineer
Principal Supportability Engineer
JAM Recruitment Ltd
Hartley Mauditt, Alton (GU34), GU35 9JL
£71 - £87 per hour + Umbrella, inside IR35
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We are seeking a highly skilled Lead Production Engineer to join a leading manufacturer specialising in advanced materials and complex mechanical processes. This pivotal role will drive optimisation and improvement across manufacturing operations, ensuring robust process controls, enhanced product quality, and streamlined production flow. * Deputise for the Production Engineering Manager when required. * Support value stream teams with day-to-day production engineering activities. * Significant experience in Process/Production Engineering within complex manufacturing. * Skilled in Production Engineering tools: Process Mapping, Yamazumi, MOST, SOPs, SPC, Value Stream Mapping, Spaghetti Diagrams. * Opportunity to shape production engine
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Role/Job Title: Senior IP Design Engineer Our client a purpose-led transformation company, who not only help businesses to transform through technology but also support them in making a meaningful difference to the people and communities they serve, work with some of the biggest brands in the UK and worldwide are looking for a Senior IP Design Engineer to be responsible for the design high-performance IP targeting FPGA/Adaptive SoC technology using System Verilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. System Verilog RTL design Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closur
Role/Job Title: Senior IP Design Engineer Our client a purpose-led transformation company, who not only help businesses to transform through technology but also support them in making a meaningful difference to the people and communities they serve, work with some of the biggest brands in the UK and worldwide are looking for a Senior IP Design Engineer to be responsible for the design high-performance IP targeting FPGA/Adaptive SoC technology using System Verilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. System Verilog RTL design Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closur