Seeking a Senior engineer to own timing constraints and synthesis for complex SoCs. Our engineers lead innovation in physical IP, AI and machine learning, cloud architecture, automotive tech, and every aspect of computing that matters. Job Summary - You will develop and validate SDCs, drive synthesis for best PPA, perform LEC for RTL/netlist equivalence, and collaborate with design, architecture, IP, and physical teams to ensure robust timing closure and high-quality deliverables. Responsibilities * Develop and maintain block- and top-level timing constraints (SDC). * Drive synthesis flows to meet PPA targets. * Perform LEC to ensure RTL-to-gate equivalence. * Define timing exceptions with design, architecture, and IP teams. * Work with technology/PD teams to integrate node-specific constraints. * Identify and communicate timing-criti
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