Industry experience of 10 years or more in layout design of analog/mixed signal circuitry. * High-speed and high accuracy Analog Front Ends comprising ADC, DAC and PLL * Candidate is required to lead and manage delivery of complex analog IP with tasks including floorplan, bump map, IO planning, lef, LVS, ERC, DRC, antenna checks. * Bachelors degree or equivalent in EE or training in layout design. * Must have direct layout experience in at least two of the following areas: High Speed ADC, DAC, high performance Phase locked loops (LC tank-based designs preferred). * Past experience of active participation in at least 2 successful complex analog silicon involving one or more of the above areas. * Deep understanding of f
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