We are looking for creative and enthusiastic IP Verification Engineers to join the team. * Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development. * Proven understanding of digital hardware verification language Verilog/Systemverilog HDL. * Skilled in one or more of various verification approaches UVM, formal, power aware verification. * Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language (preferably ARM). * Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support. * Knowledge of IP/SoC Verification Flow and strategy. * Clock domain crossing verification. * Skilled in UPF Power Aware verification.
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